Fiabilité du signal des circuits logiques combinatoires sous fautes simultanées multiples

Integrated circuits have known a constant evolution in the last decades, with increases in density and speed that followed the rates predicted by Moore's law. The tradeo s in area, speed and power, allowed by the CMOS technology, and its capacity to integrate analog, digital and mixed components, are key features to the dissemination of integrated circuits on the eld of telecommunications. In fact, the progress of the CMOS technology is an important driver for telecommunications evolution, with the continuous integration of complex functions needed by demanding applications. The evolution scenario of the consumer electronics industry is a result of the fairly easy gains obtained with CMOS scaling, but this scenario is about to change, as scaling approaches some limits that make further improvements more di cult and even unpredictable. The continuous reduction in the dimensions of integrated circuits has raised some serious problems to the implementation of nanometric circuits, like power consumption and dissipation, current leakage and parametric variations. Many of these problems lead to a reduction in the yield and the reliability of CMOS devices, what can seriously compromise the gains attained with technology scaling. To cope with these problems, work-around solutions are necessary, and more speci cally, the sensibility of the circuits to transient faults must be improved. Historically, transient faults were a concern in the design of memory and sequential elements only, and the protection of these elements is fairly simple and do not impose critical overheads, due to the static nature of the data involved. On the other way, the susceptibility of combinational blocks to transient faults, e.g., soft errors, thermal bitips, parametric variations, etc, increases as a side e ect of technological scaling, and the protection of these blocks poses some problems to the designers. Known solutions are the use of fault-tolerant approaches, like modular redundancy and concurrent error detection but these solutions lead to important overheads in terms of implementation area, propagation time and power consumption. The referred solutions are traditionally targeted to mission critical applications, where reliability improvement and fault secureness are the main design objectives, and the resulting overheads can be accepted. In the case of mainstream applications, other design objectives are privileged and the implementation of these fault-tolerant approaches must be bounded by a detailed cost-bene t analysis. Given the overheads associated with the traditional fault-tolerant approaches, alternative solutions based on partial fault tolerance and fault avoidance are also being considered as possible solutions to the reliability problem. These approaches are based on the application of fault tolerance to a restricted part of the circuit or hardening of individual cells, allowing ne-tuned improvements on the reliability and limiting the concerned overheads. The choice of what reliability improvement method is better suited for a given application is not simple as the problem involves multi-criteria optimization. In this context, a fast and accurate evaluation of circuit's reliability is fundamental, to allow a reliability-aware